Digital Electronics

	*Digital Electronics*
	syllabus resources What’s nEEw?

Date	Notes	Class Activities
Please share your thoughts about this class (it’s anonymous)
5/29		Graduation 4pm
5/23		P7 final period (8:15 – 10:15) study guide Choose between written 60%, Lab 1 +40%, Lab 2 +10% written 95%, Lab 1 +5% you are welcome to take it with P6 on 5/21 if your P6 teacher is OK with it.
5/21		P6 final period (10:25 – 12:25) study guide see 5/23 P7 final period for grading
5/20	C day	Moore’s Law, Amdahl’s Law, Dennard Scaling Hennessy & Patterson Turing Award Lecture (28:11-29:55 35:56-43:08) podcast Hennessy & Patterson (Turing Award winners) RISC vs CISC [24:52 – 27:32] CS Students / FPGA [29:34 – 31:38] State of the Field [35:05 – 41:15]
???		finish … Lab3 (Part V) Flip-flops
???		Lab3 (Part V) Flip-flops
5/17		finish …Lab2: Numbers and Displays
5/16	Turing Awards 2015 2016 2017 2018	Lab2: Numbers and Displays do Parts I & III first and then do Part II if you have time [40%] I. two 4-bit binary to two 7seg (a) optimized logic (b) simple logic [80%] III. 4-bit Ripple Carry Adder [100%] II. 4-bit binary to 2-digit decimal
5/14		continued… Lab1: Switches, Lights, and Multiplexers III. 3 to 1 Mux IV. 7 Segment Display Section 4.3 Using the 7-Segment Display V. 7 Segment Display 3 to 1 Mux VI. SKIP
5/9		Lab1: Switches, Lights, and Multiplexers (download PDF for teacher comments) use DE1 Lab Guide to setup project and assign pins I. Switches to LEDs II. 2 to 1 Mux
5/7		a breadboard LALU? video 1 general 1:07-3:24 clock 5:34-6:15 video 2 programming 7:08-9:16 execution 13:43-15:15 Verilog ~~Testbench~~ ~~lights tested~~ ~~5 points, skip this if you are behind~~
AP Testing week 1 May 6-10 week 2 May 13-17
5/3	DE1 Lab Guide DE1 User’s Manual	Using the DE1 board DE1 XOR or NAND
5/2	FPGA software	Digital Design Flow & FPGAs Intro to Altera Quartus II & Modelsim download pdf XOR gate simulation NAND gate simulation An example where FPGA’s are used in a university class & lab University of California CSE 141L: Introduction to Computer Architecture Lab prerequisites CSE 140 Lab 1 (uses Altera & Modelsim) – an example of what one of your university lab classes may look like in a year or two
Digital Design
4/30		ARM Architecture Procedure Call Standard finish … ARM
4/25		ARM Functions, Stacks, and Frames calc Function
4/23		ARM Instruction Set (Conditional Execution, Branches) ARM: Find the Max
4/18		ARM Instruction Set (Data Processing, Load/Store) Logical ARM patents
ARM Programming
4/16		finish … LALU
4/12	UIL Regionals @ UTSA	Make a T568B Ethernet Cable Platinum Tools EZ-RJ45 Crimp Tool [5 pts]
4/11	English II EOC	LALU Postmortem LALU Performance finish … max of ? numbers
4/9	English I EOC & SAT	Class meets in Room 247 (P6 Mr Mueller proctoring) over half the class is testing
4/4		continue … max of ? numbers
4/2		continue … max of ? numbers
3/29	end of 5th 6 weeks
		Design of the RISC-V Instruction Set Architecture Andrew Waterman dissertation @ UC Berkley
3/29		Conditional Jumps, etc. jmpNeg, loadA test conditional jump & loada LALU: Find the max [80%] max of 7 numbers [90%] max of 100 numbers [100%] max of 100 numbers (with possible overflow) SuperBONUS sort the numbers in data memory
3/28		finish… test jmp, continuous fibonaccis
3/26	CTE survey	Jump & Nop jmp, nop instructions test jmp continuous fibonaccis

3/14		Intel x86 finish… 11 fibonaccis
3/12		Pipelining continue… 11 fibonaccis
3/8		Store store instruction 11 fibonaccis
3/7	jeopardy (Computer Science)	finish … add ten numbers in data memory
3/5	Spreadsheet AP assembler	Load & Exchange add Data RAM, Instruction Register, Decoder load, exchange instructions add ten numbers in data memory
2/28		finish … Spice & Microarchitecture (Part 1)
2/26	RPN Calculator HP15C (click on pic) (5 x (10-3))/(7-2) -1² = (-1)²	Memories – Program Memory & Program Counter add a Program Counter, Program Memory add and subtract 4 times
2/22		Amid challenges, chipmaker AMD … pipeline spreadsheet (clock skew effect) Microarchitecture
Microarchitecture (LALU)
2/21		finish sequential logic today & after lecture on 2/22
2/19		Path Delay Path Delay simulations [5 pts] Interview Question #1 (Standard cells TSMC 0.18) Why does a standard cell library have both a NAND, INV, and an AND?
2/14	Microchip / Briggo Field Trip 10:00am – 2:00pm
2/12	Spice Summary Latch & Flip-Flop timing	Latches (2019 – slides 1-2, 12-16 only) ~~D-latch simulations 1-3 [85%] simulation 4 [100%]~~ Flip-Flops D Flip-Flop simulations 1-4
Sequential Logic
2/8	end of 4th 6 weeks
2/7		finish up all adder related stuff
2/5		Overflow Two Ways [2 pts] do not work on this unless you are caught up with the class.
2/1		finish … Binary Subtraction and Overflow
1/31	Binary Addition & Subtraction	Binary Subtraction & Overflow 16 bit Adder & Subtractor
1/29		finish … Soldering
1/24		Soldering Soldering Video Soldering Project 85% if DONE, 100% if WORKING or thoroughly debugged Soldering is Easy
1/22		Comparison Between Various Types of Adder Topologies look @ references Carry Lookahead Adder only worth 5 points, so finish everything else before attempting this
1/17		Standard Cells finish … 8/16-bit Carry Select Adder
1/15		Quiz Questions Carry Select Adder 8-bit Carry Select Adder 16-bit Carry Select Adder label with timing
1/11		Multiplexers 4-to-1 Mux #1 4-to-1 Mux #2
1/10	Karnaugh Maps, etc	finish … Ripple Carry Adder
1/8		Ripple Carry Adder 4-bit Ripple Carry Adder 8-bit Ripple Carry Adder 4 bit-adder Domino Video Domino AND and XOR gate (10:42 adder)
Make sure Santa brings you the FA0, FA1, FAopt1, FAopt2 circuits
12/20	end of 3rd 6 weeks
12/18 12/20		Semester Exam 12/18 Period 6 (2nd period of the day) 12/20 Period 7 (1st period of the day) MIDTERM topics
12/14	C-day Euler’s Disk	Lab & drawer clean up look at calculators solder lights
12/13	Boolean Logic	finish … Cout Optimization
12/11		Cout Optimization Full Adder Circuits
12/6		Half & Full Adders XOR equivalence FA0 circuit FA1 circuit Full Adder sum & carry out equivalence
Binary Adders
12/4		Field Trip makeup day makeup work for the other class you missed for the field trip
11/30	Samsung Field Trip 10:00am – 2:00pm photo release form
11/29	FIELD TRIP ON FRIDAY	Digital vs Analog MIDTERM topics finish … 4-input Seven Segment 0-9
11/27	FIELD TRIP ON FRIDAY teacher email	continue … 4-input Seven Segment 0-9 Video Domino AND and XOR gate (6:10-9:30)

11/15	Seven Segment 0-9 Minimization	Karnaugh Maps 4-input Seven Segment 0-9 finish … 2-input Seven Segment 0-3
11/13		continued … 2-input Seven Segment 0-3
11/9		Boolean Algebra Socrative 2-input Seven Segment 0-3 simulate simplified logic circuit simulate min-transistor circuit build min-transistor circuit
11/8	Binary & Hex Conversion 4-func calculator	HP15C (5 x (10-3))/(7-2) -1^2 = ? continued … Basic Seven Segment Display Circuits Truth Table
11/6		Truth Tables & Boolean Expressions Truth Table “hex” Values LASA{CS} ASK Hello 7-Segment Hello SOP Partly Simplified DeMorgan’s (in next lecture)
11/2	end of 2nd 6 weeks
11/1		Logisim Help -> Tutorial 1st four sections of Help -> User’s Guide -> Subcircuits -> Creating circuits XOR symbol & circuit
10/30	Transistors & Spice	finish … 7-segment Arduino 0-F
10/26		7-segment Displays 7-segment Arduino 0-F truth table circuit logic analyzer
10/25	odometer Conversion calculator	Data Representation – Number Systems Magic Cards (cards) Exponential Growth (binary vs decimal) spreadsheet Decimal, Binary, Hexadecimal Decimal and Binary Number systems Hexadecimal Number system Questions 1-5 lasacs Hex to Binary Shortcut Number Conversion worksheet
Combinational Logic Circuits
10/23		Samsung 7nm EUV CMOS Logic Gates finish … NAND and NOR gate simulations
10/18		NAND and NOR gates (Part II) continue … NAND and NOR gate simulations
10/16	Spice Summary	NAND and NOR gates (Part I) NAND [80%] and NOR [100%] gate simulations
10/11		LASA{CS}ASK 7404 Hex Inverters inverter & ring oscillator measurements [100%]
10/9		Ring Oscillator Ring Oscillator simulation [85%]
10/4		Buffers Buffer simulation[70%]
10/2		Review Spice Summary Samsung Announces $4B Investment Understanding IC Costs List of Intel Fabs How Intel Makes a Chip (3:11) How do they make Silicon Wafers and Computer Chips (9 min) check for understanding – Draw NMOS/PMOS, inverter (a) schematic (b) symbol (c) Vin vs Vout finish … Inverter Simulations NACLO (North American Computational Linguistics Olympiad)
9/28	end of 1st 6 weeks
9/28	Spice Summary ngspice Manual	Inverter Design & Simulation Inverter Simulations
9/27		NMOS & PMOS transistors How does a transistor work? (6:00) Coolspice Inverter Simulation installing & running ngspice
9/25		MOSFET transistors Build a Transistor Step by Step (groups of 2) NMOS Transistor Simulation
Transistor Circuits
9/13 9/14 9/18 9/20	9/20 CTE Counselors	Arduino 101 (Projects 1-7) Projects 1-3: 80% 4-5: 90% 6 or 7:95% all 7:100%
9/11	capturing oscilloscope screen	Using an oscilloscope Oscilloscope
9/6	Spice Summary arduino issues	Introduction to a SPICE simulator (CoolSPICE) RC Circuit Spice Simulation Arduino 101 (Get Started)

09/4		Capacitors Inductors (for reference only) falstad -> Capacitor finish … Light up an LED
8/30	Basic Electricity & Ohm’s Law calculator	fritzing demo Light Emitting Diodes (LED) Light up an LED
8/28	measuring current	next time … Quiz Basic Electricity & Ohm’s Law for the Quiz finish … Series and Parallel Resistance
8/24		Resistive Circuits & Ohm’s Law Ohm’s Law Practice (optional) Power, Multimeter, Breadboard Arduino 101 (POWER – slides 1-11) Series and Parallel Resistance
8/23	falstad	seating chart Welcome to BLEND Check for Understanding finish Current, Voltage, Resistance Basic Resistive Circuits
DC Circuits
8/21	Euler’s Identify & Euler’s Formula	Getting Started The goal today is to get an overview of the course, go over class expectations, as well as setup and learn some of the tools we’ll be using. about teacher lasacs.com syllabus honor code no computer games on classroom computers at any time Student survey Parent survey Signature lasacs.com/ask/222 (bookmark, ?) Google Classroom snipping tool What’s nEEw Moore’s Law and Dennard Scaling Computer Science Club Women in Computer Science Club (WICS) Hack Club UIL Competitions/CTFs/NACLO, Cyberpatriot, Online Challenges Peer Tutoring In File Explorer Organize -> Folder and search options -> View Tab -> Uncheck “Hide extensions for know file types” [email protected] include Period # in email subject and name in e-mail body Current, Voltage, Resistance

Digital Design

ARM Programming

Microarchitecture (LALU)

Sequential Logic

Binary Adders

Data Representation – Number Systems

Combinational Logic Circuits

Transistor Circuits

DC Circuits

Getting Started