Digital Electronics

	Digital Electronics
	syllabus resources What’s nEEw? AISD✓ CANVAS✓ soapbox (how) Rm506

sign-out videos Turn in in-person BLEND CSAC P1 P2
Date	Notes	Class Activities
class survey
5/23A FINALS		FPGA LABS (1) XOR and NAND simulation (2) DE1 XOR or NAND (3) lights tested (4) Lab 1 (5) Lab 2 APs is how many Digital Electronic classes you missed due to an AP test. Final Exam Grade based on DEs missed for APs is the higher of Semester Average plus the value below missed <= 1, (none) -4 (1) -3 (2) -2 (3) -1 (4) 0 (5) +2 missed <= 2, (none) -3 (1) -2 (2) -1 (3) 0 (4) +2 missed <= 3, (none) -2 (1) -1 (2) 0 (3) +2 The grade below missed <= 1, (none) 0 (1) 60 (2) 70 (3) 80 (4) 90 (5) 100 missed <= 2, (none) 0 (1) 70 (2) 80 (3) 90 (4) 100 missed <= 3, (none) 0 (1) 80 (2) 90 (3) 100
5/21A 4A21		ALL Altera University Labs FPGA Labs 1 2 3 5 Timing skipped 4 6 7 8 9 10 11 12 these and LOTS more at Intel FPGA Academy
5/19A 4A20		lab Lab2: Numbers and Displays [] do Parts I & III first and then do Part II if you have time [40%] I. two 4-bit binary to two 7seg (a) optimized logic (b) simple logic [80%] III. 4-bit Ripple Carry Adder [100%] II. 4-bit binary to 2-digit decimal
5/14A 4A19		continued… Lab1: Switches, Lights, and Multiplexers III. 3 to 1 Mux [75%] IV. 7 Segment Display [90%] Section 4.3 Using the 7-Segment Display V. 7 Segment Display 3 to 1 Mux [100%] VI. SKIP
5/12A 4A18		lab Lab1: Switches, Lights, and Multiplexers (download PDF for teacher comments) use DE1 Lab Guide to setup project and assign pins I. Switches to LEDs [25%] II. 2 to 1 Mux [50%]
5/09A 4A17	Compiler Explorer	Verilog Testbench lab lights tested
5/07A 4A16	DE1 Lab Guide DE1 User’s Manual	Using the DE1 FPGA board lab DE1 XOR or NAND
5/05A 4A15	FPGA software	The History of the FPGA Digital Design Flow & FPGAs Altera Quartus II & Modelsim lab XOR and NAND simulations XOR gate simulation [70%] NAND gate simulation [100%] An example where FPGA’s are used in a university class & lab University of California CSE 141L: Introduction to Computer Architecture Lab prerequisites CSE 140 Lab 1 (uses Altera & Modelsim) – an example of what one of your university lab classes may look like in a year or two
Digital Design
4/30A 4A14		ARM Architecture Procedure Call Standard finish … ARM optional … RISC-V ISA write a RISC-V program (reference) simulator #1 simulator #2
4/28A 4A13		ARM Functions, Stacks, and Frames video lab calc Function [5 pts 5/7] BONUS recursion???
AP Testing Form
4/25A 4A12		how is the multiply instruction decoded? workday patent interview questions
4/23A 4A11		ARM Conditional Execution and Branches video lab ARM: Find the Max [10 pts 4/29 7# [70%] 100 half [80%] 100 full [90%] 100 full <= 11 instructions [100%]]
4/21A 4A10	VisUAL 2	ARM Data Processing and Load/Store video ARM Intro [10 pts 4/28] lab Max of 3 [70%] lab Logical [>= 9 instr 90%, <=8 instr 100%] ARM patents
ARM Instruction Set
4/16A 4A09		A-DAY Biology EOC (9), WHAP Mock AP (10), US History EOC (11) all A-Day classes in afternoon 40 minutes each Key Ideas in High Throughput Processing: Superscalar, SIMD, Multi-Core, and Multi-threading 88110 Instruction Sequencer tinytapeout.com Digital Design Guide Wowki
4/14A 4A8		Find the Max (in JAVA) LALU Postmortem & LALU 2.1 lab LALU Performance [3 pts 4/19] lab LALU 2.1 [BONUS] BONUS implement the subtraction based version of Euclid’s GCD algorithm and optimze it to find the GCD of 1818h & 2727h in < 50 cycles (and 1234h & 789Ah in < 420 cycles). Numbers are in memory, leave GCD in a register.
	EOCs	Tue 4/8 Eng I (9th-AM) Wed 4/9 Eng II (10th-AM) Wed 4/16 Bio (9th-AM) USH (11th-AM): short classes in PM
4/9A 4A07		finish … Find the max Modern CPU Architectures – Part 2 1:30 – 12:54 Mathematical mistake in video?
4/07A 4A06		continue … Find the max Design of the RISC-V Instruction Set Architecture Andrew Waterman dissertation @ UC Berkley
4/04A 4A05		Conditional Jump [20 pts 4/16] lab Test Conditional Jump [50%] lab LALU Find the Max submit code P1 P2 max of 7 numbers [70%] in less than 22 instructions & 74 cycles [80%] as low as 16 instructions is possible max of 100 numbers [90%] max of 100 numbers (with possible overflow) [100%] BONUS #1 – sort the numbers in data memory BONUS #2 – compute & store the Collatz sequence in memory (e.g. starting with 27)
4/02A 4A04		workday
3/28A 4A03		Jump Speed Up lab Test jump speed up [80%] lab Continuous Fibonaccis [100%]
3/26A 4A02		Pipeline Hazards & Jump [15 pts 4/4] lab Test jump & nop [70%]
3/24A 4A01		Intel x86 Pipelining finish …Fibonaccis

3/14	end of 9 weeks
3/12A 3A21		Storing Data lab Fibonaccis [10 pts 4/02]
⮟ last assignments for this 9 weeks ⮝ first assignments for next 9 weeks
3/10A 3A21	2024 Turing Award	finish … First 4 Instructions
3/05A 3A20	assembler.py	Loading Data lab First 4 Instructions [15 pts 3/14]
3/03A 3A19		Workday
2/28A 3A18		Instruction Register & Decoder lab First Program LAST Time [10 pts 3/10]
2/26A 3A17	get caught up with LALU	finish … Soldering Project & clean up
2/24A 3A16	get caught up with LALU	Soldering lab Soldering Project [10 pts 3/5] 85% if DONE, 100% if WORKING or thoroughly debugged
2/21A 3A15		Silicon Labs Field Trip (9:30am – 1:30pm) Thank You Silicon Labs!!!
2/19A 3A14	Latch & Flip-Flop (no spice) answer format answer example [12 pts, 14 possible]	UIL Calculator Applications (70 questions in 30 minutes) RPN Calculator HP15C (8 x (10-3))/(6-2) LALU workday
2/12A 3A13	jeopardy 21-25	Program Memory & Program Counter lab First Program [10 pts 2/26]
2/10A 3A12	jeopardy 16-20	lab Test Registers [5 pts 2/19]
2/07A 3A11	jeopardy 11-15	Amid challenges, chipmaker AMD … clock skew effect Microarchitecture Introduction lab R0 & R1 [5 pts 2/19]
Microarchitecture (LALU)
2/05A 3A10	50 min class culture day jeopardy 6-10	finish Sequential Logic Unit Max Frequency [2 pts 2/12]
2/03A 3A09	jeopardy 1-5	Path Delay lab Path Delay Simulations (ind) [5pts 2/10] Q1-Q4 [70%, 80%,90%,100%]
1/31A 3A08	Binary Addition & Subtraction	once again … Flip-Flops (setup, hold, clk-to-q, spice, demo)
1/27A 3A07		Flip-Flops Latch & Flip-Flop timing [5 pts 2/3] answers lab D Flip-Flop simulations (pair) [10 pts 2/7] Simulation 1 [50%], Simulation 2 [70%], Simulation 3 [90%], Simulation 4 [100%]
1/22A 3A06	Spice Summary	Latches lab D-latch simulations (pair) [10 pts 1/29] Simulation 1 [50%], Simulation 2 [70%], Simulation 3 [90%], Simulation 4 [100%]
Sequential Logic
1/17A 3A05		lab Overflow Two Ways [2 pts 1/27]
1/15A 3A04	2s comp oddities	Binary Subtraction & Overflow lab 16-bit Adder & Subtractor [15 pts 1/27] Part 1 using logisim adder [70%] Part 2 using your CSA adder [100%]
1/13A 3A03	weird number	With a partner – make a copy of What to add? What to add? (solution & questions) Negative Binary Numbers (Two’s Complement) Twos Complement Numbers [5 pts 1/22] answers
1/10A 3A02	fabs in Austin	Carry Lookahead Adder lab Carry Lookahead Logic [5 pts 1/17] [70%: #1 80%: #2 90%: #3 100%: #4] BONUS – Build a faster 16-bit adder. Who can get the fastest? see this paper for a variety of adder topologies
1/8A 3A01	tinytapeout	Standard Cells finish lab Carry Select Adder

12/20	end of 9 weeks
12/18A		Midterm Exam (Open “notes” – slides and labs) [70 pts] 32 multiple choice (2.4pts each, 76.8pts possible) [30 pts] 6 short answer (5pts each, partial credit)
12/16A 2A16	hack-a-day PFLASA post	Carry Select Adder lab Carry Select Adder [15 pts 1/13] [80%: adds, 90%: ~timing, 100%: correct]
12/11A 2A15	types of engineering oden	Multiplexers lab 4-to-1 Multiplexer [10 pts 1/8]
⮟ last assignments for this 9 weeks ⮝ first assignments for next 9 weeks
12/9A		finish … Ripple Carry Adder BONUS Make an Ethernet Cable [3 pts] Turing Award (Ethernet) Turing Award by Year
12/6A 2A13	Domino Adder (13:22 adder)	Ripple Carry Adder lab 8-bit Ripple Carry Adder [10 pts 12/16] [80%: adds, 90%: ~timing, 100%: correct]
12/04A 2A12	Logic, Truth Tables, Karnaugh Maps, etc	Boolean Algebra Practice Quiz MIDTERM topics Intel FDIV bug Hubble KC Challenger
12/02A 2A11		Full Adder Optimization lab FAopt1 & FAopt2 [5 pts 12/9] Boolean Logic [5 pts 12/9] answers
12/01	Advent of Code *win a LASA{CS} T-shirt* Read From File UIL – Things to Know

11/20A 2A10	Timing & Labels	Half & Full Adders [10 pts 12/4] lab FA0, FA1, Equivalence FA0 [70%] FA1 [90%] XOR equivalence [95%] Sum & Count equivalence [100%]
Binary Adders
11/18A 2A9	minimum clicks	finish lab 4-input 7-Segment 0-9 Domino INV, AND, XOR gates (6:05-9:52)
11/15A 2A8	light switch Nov 15, 1971	Karnaugh Maps lab 4-input 7-Segment 0-9 [15 pts 12/02] 1. 7- Segment 0-9 Minimization answer sheet (make copy, don’t turn in) 2. simplified SOP circuit [75%] 3a. DeMorgan circuit [90%] 3b. DeMorgan minus 2 gates [100%] 4. timing from 6 to 7 [BONUS + 2pts]
11/13A 2A7	UT ECE (pdf pptx)	finish lab 2-input 7-Segment 0-3 HW
11/11A 2A6		Boolean Algebra (Part2 33-end) Practice (with a partner) (10 minutes) lab 2-input 7-Segment 0-3 HW (pairs #6) [15 pts 11/20] make copy of answer sheet simplified boolean equations [50%] simulate min-transistor circuit [70%] simulate 74xx circuit [85%] build min-transistor circuit [100%]
11/6A 2A5	Binary & Hex Conversion	Boolean Algebra (Part1 1-32) NAND game2 – apply DeMorgan’s to the XOR gate so it takes only 16 transistors BONUS +2 pts build the ‘DeMorganized’ LASACS circuit on a breadboard finish lab LASACS 7-Segment
11/04A 2A4	SOP logo	CMOS Logic Gates (from previous unit) Truth Table “hex” Values #2 continue lab LASACS 7-Segment Truth Table [5 pts 11/11] answers
10/30A 2A3		Logic Circuits, Truth Tables & Boolean Expressions Truth Table “hex” Values #1 lab LASACS 7-Segment [10 pts 11/11] SOP LASACS truth table [70%] Partially Simplified [90%] DeMorgan’s (after Boolean Algebra lecture) [100%]
10/28A 2A2		finish … 7-segment Arduino 0-F Logisim-Evolution Berkley CS61C Cornell CS3410 Duke ECE/CS 250 Help -> Tutorial 1st four sections of Help -> User’s Guide -> Subcircuits -> Creating circuits lab XOR [5 pts 11/4] XOR symbol & circuit [80%] NAND game1 – XOR (INV/AND/OR only) [100%]
10/23A		Do it again
10/21A 2A1	Transistors Inverters Buffers Spice [14 pts]	7-Segment Displays 7-segment Displays lab 7-segment Arduino 0-F (pairs #5) [10 pts 10/30] tinkercad [75%] circuit [90%] logic analyzer [100%]
Combinational Logic Circuits
10/18	end of 9 weeks
10/18A 1A20	odometer “The Martian” hexadecimal scene binary game	Data Representation – Number Systems Magic Cards (cards) Exponential Growth (binary vs decimal) spreadsheet Decimal Binary Hex Decimal and Binary Number systems Hexadecimal Number system Questions 1-5 lasacs Decimal, Binary, Hexadecimal Tables Hex to Binary Shortcut Number Conversion worksheet answer key [5 pts 10/25] Radiolab Bit Flip (1:01 – 10:50) whole podcast
10/16A 1A19		NAND gate lab NAND gate simulation Part 1 & 2 [BONUS +3 pts] NOR gate lab NOR gate simulation [BONUS +3 pts]
10/11A 1A18		Workday lab Arduino 101 (Projects 3 & 4) [BONUS +1.5pts each]
10/9C	PSAT	Z2 homemade silicon chip (5:46) Periods 1-4 meet for 30 minutes each in afternoon
10/7A 1A17	555 walking	lab Using 7404 Hex Inverters (pairs #4) [10 pts 10/23] answer sheet
⮟ last assignments for this 9 weeks ⮝ first assignments for next 9 weeks
10/2A 1A16		How Intel Makes a Chip (3:11) LASA{CS}ASK Ring Oscillator lab Ring Oscillator simulation [5 pts 10/18]
9/30A 1A15		How do they make Silicon Wafers and Computer Chips (0:41-8:30) Buffers lab Buffer Simulation [5 pts 10/18]
9/27A 1A14		Transistor Evolution Inverters lab Inverter Simulations (pairs #3) [10 pts 10/16]
9/25A 1A13		NMOS & PMOS transistors Inverter Sizing [5 pts 10/2]
9/23A 1A12	spice summary & debug Dr. Patt 2	finish spice from last time (30 min) start making rectangles when done with spice Photolithography (last 60 minutes) lab Build a Transistor out of Play Doh Step by Step (groups of 2 or 3) {5 pts 9/23}
9/18A 1A11	LEDs & Capacitors [13 pts] complex invention	MOSFET transistors (Introduction) MOSFET Transistor (How It Works) lab NMOS Simulation [5 pts 9/25] [90%] size of transistor for more current [100%] threshold voltage to nearest 1/10th volt
Transistor Circuits
9/16A 1A10	college NPV	finish Oscilliscope lab lab Arduino 101 (Projects 1 & 2) (groups #2) [10 pts 9/23]
9/13A 1A9	oscilloscope1 left clickoscilloscope2 scrollarduino issues	Arduino 101 (Get Started) lab Oscilloscopes Using an Oscilloscope (groups #2) [10 pts 9/23]
9/11A 1A8	series or parallel spice summary & debug	LED video Introduction to a Spice simulator (ngspice) installing ngspice finish lab Simulating RC Circuits (ind) ngspice Quiz 2 Capacitors & LEDs (PRACTICE)
9/9A 1A7		Measuring Voltage & Current (GoSoapBox) finish … Light up a LED Capacitors Inductors (for reference only) lab Simulating RC Circuits (ind) {10 pts 9/18} Desmos ngspice (next time)
9/4 1A6	Electricity, Resistive Circuits, Multimeter, Breadboardretake up 80%	Light Emitting Diodes (LEDs) lab Light up a LED (pairs #1) {10 pts 9/16} LED Datasheet
8/30 1A5		Measuring Resistance (GoSoapBox) finish … Series and Parallel Resistance
8/28 1A4	What’s nEEw?	Arduino 101 (POWER – slides 1-12) Power, Multimeter, Breadboard Tinkercad (Introduction) lab Series and Parallel Resistance (pairs #1) {15 pts 9/9}
8/26 1A3	What’s nEEw?	Resistive Circuits & Ohm’s Law falstad circuit simulator (demo) lab Basic Resistive Circuits (20 minutes) (pairs #0) {10 pts 9/3}
8/23 1A2		seating chart (meet your neighbors) Reporting Values Current, Voltage, Resistance lasacs
DC Circuits
8/21 1A1		Getting Started teacher lasacs.com: courses calendar Peer Tutors puzzles syllabus Women in Tech & Engineering attendance, seating chart (next class day) Room 506 (hall pass, lost & found, scratch paper) lasacs.com/ask/506 ? seniors – this class is busy until the end of 2nd semester [email protected] put *Period #* and *name* in email subject BLEND (Can you see class? Turn off Color Overlay!!!) LASA Honor Code & Syllabus File Explorer (View -> File name extensions) LASA{CS} CLUBS First Day LASACS evacuation route evacuation meetup location class text book Welcome to Digital Electronics Moore’s Law, etc.

Digital Design

ARM Instruction Set

Microarchitecture (LALU)

Sequential Logic

Binary Adders

7-Segment Displays

Combinational Logic Circuits

Transistor Circuits

DC Circuits